1. Field of the Invention
The present invention relates to a dual sampling/pixel gain amplifier (CDS/PxGA) circuit with a shared amplifier, and more particularly, to a dual CDS/PxGA circuit for adjusting a gain of an amplifier based on capacitance.
This work was supported by the IT R&D program of MIC/IITA. [2006-S-006-02, Components/Module technology for Ubiquitous Terminals].
2. Discussion of Related Art
A charge coupled device (CCD) is a device for converting an image into an electrical signal, and has been widely used in apparatus such as camcorders, digital cameras, etc., which store images in a digital data form. In converting the image into the electrical signal, the CCD receives data levels and reset levels from a plurality of pixels to output them in a form of a single-ended signal. In order to minimize influence of reset noise generated between the respective pixels in such a process, a correlated double sampling (CDS) circuit subtracts the data level from the reset level to generate output signals for the respective pixels.
FIG. 1a illustrates an image processing process using a conventional CDS circuit. Referring to FIG. 1a, an output signal of each CCD pixel can be classified into one of a red signal R, a green signal G, or a blue signal B based on a color filter of the pixel, wherein the respective color signals can have different magnitudes.
If output signals of the CDS circuit are amplified by a variable gain amplifier (VGA), the respective color signals obtain the same amount of noise. Therefore, the respective color signals having the different magnitudes have different signal to noise ratios (SNRs). That is, since a signal amplification range of the VGA is limited by means of the largest signal (G), a relatively small signal (B) is not sufficiently amplified, and thus the SNR thereof becomes small.
Thereafter, amplified signals are converted into digital signals through an analog to digital converter (ADC), and a digital signal processor (DSP), as a final stage, adjusts the respective color signals containing the noise to the same magnitude. Since the DSP can not reduce the magnitude of the noise generated in an analog stage, the blue signal B contains more noise than the green signal G or the red signal R, among the signals passing through the DSP.
In order to solve such a problem, it is necessary to adjust the CDS output signals having the different magnitudes to the same magnitude before they are provided to the VGA stage. Referring to FIG. 1b, a pixel gain amplifier (PxGA) amplifies the CDS output signals with different gains to adjust the CDS output signals having the different magnitudes to the same magnitude. Thus, it is possible to improve the SNR of the output signal processed by the DSP in the image processing process, by adding the PxGA after the CDS.
Such a PxGA can be implemented using a programmable amplifier having a gain adjustable according to pixel output. Accordingly, a CDS/PxGA circuit capable of simultaneously performing both functions of the CDS and the PxGA using a capacitance-based programmable amplifier has been proposed.
FIG. 2a is a circuit diagram of a conventional CDS/PxGA circuit, and FIG. 2b is a timing diagram of the conventional CDS/PxGA circuit.
Referring to FIGS. 2a and 2b, when a clock q1 becomes high, a switch for connecting an output terminal of an operational amplifier (OP AMP) to a negative input terminal thereof is closed, a sampling capacitor (Cs) 202 samples a reset level Vreset applied to an input unit 201, and a feedback capacitor (Cfb) 203 samples reference voltage. In an exemplary embodiment, the reference voltage can be ground voltage.
Next, when a clock q2 becomes high, the sampling capacitor 202 samples a data level Vdata applied to the input unit 201, and the feedback capacitor 203 is connected to the output terminal of the OP AMP 204. Accordingly, charges move from the sampling capacitor 202 to the feedback capacitor 203 so that an output signal of an output unit 205 has a value of (Cs/Cfb)/(Vreset−Vdata). Therefore, the conventional CDS/PxGA circuit can adjust gains for the respective pixel outputs using capacitance values of the sampling capacitor and the feedback capacitor.
However, since the conventional CDS/PxGA circuit uses only one input, it must receive both of reset signals and data signals via one sampling capacitor. Therefore, output valid time OUTPUT VALID becomes a half of a period T of the clocks q1 and q2. This requires an operational amplifier having a twice higher speed than the period T of the clocks q1 and q2 and increases power consumption.
In addition, the conventional CDS/PxGA circuit cannot implement a gain less than 0 dB, and therefore it can amplify a small signal to a large signal but cannot attenuate the large signal to the small signal, and cannot reflect offset of the CCD output signal in the output signal of the CDS/PxGA circuit.